A physically unclonable function (PUF) technology is a novel method for protecting the data of a semiconductor chip. That is, the use of the PUF technology can prevent the data of the semiconductor chip from being stolen. In accordance with the PUF technology, the semiconductor chip is equipped with a random code generator for providing a random code. The random code is a unique identity code (ID code) of the semiconductor chip to achieve the protecting function.
Generally, the PUF technology acquires the unique random code of the semiconductor chip according to the manufacturing variation of the semiconductor chip. This manufacturing variation includes the semiconductor process variation. That is, even if the PUF semiconductor chip is produced by a precise manufacturing process, the random code cannot be duplicated. Consequently, the PUF semiconductor chip is suitably used in the applications with high security requirements.
Moreover, U.S. Pat. No. 9,613,714 disclosed the use of a one time programming memory cell (also referred as an OTP cell) to form a random code generator so as to generate a random code.
The random code generator comprises an OTP cell. The OTP cell comprises two storing circuits. Each storing circuits comprises an antifuse transistor. The OTP cell is also referred as a physically unclonable function cell (or a PUF cell). Each PUF cell stores one bit of a random code.
Generally, if the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor is lower than a withstanding voltage, the antifuse transistor is in a high resistance state. Whereas, if the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor beyond the withstanding voltage, the gate oxide layer of the antifuse transistor is ruptured and thus the antifuse transistor is changed from the high resistance state to a low resistance state.
Moreover, U.S. Pat. No. 9,613,714 disclosed various PUF cells for generating the random code. FIG. 1A is a schematic circuit diagram illustrating a conventional PUF cell. FIG. 1B is a bias voltage table illustrating the bias voltages for programming and reading the conventional PUF cell of FIG. 1A.
As shown in FIG. 1A, the PUF cell c1 comprises a first select transistor S1, a first antifuse transistor A1, a second select transistor S2 and a second antifuse transistor A2. A first source/drain terminal of the first select transistor S1 is connected with a bit line BL. A gate terminal of the first select transistor S1 is connected with a word line WL. A first source/drain terminal of the first antifuse transistor A1 is connected with a second source/drain terminal of the first select transistor S1. A gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. A first source/drain terminal of the second antifuse transistor A2 is connected with a second source/drain terminal of the first antifuse transistor A1. A gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. A first source/drain terminal of the second select transistor S2 is connected with a second source/drain terminal of the second antifuse transistor A2. A gate terminal of the second select transistor S2 is connected with the word line WL. A second source/drain terminal of the second select transistor S2 is connected with the bit line BL.
Please refer to FIG. 1B. During a program cycle, a ground voltage (0V) is provided to the bit line BL, a select voltage Vdd is provided to the word line WL, and a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2. Moreover, during the program cycle, the bias voltage provided to the word line WL may be in the range between the select voltage Vdd and a voltage Vdd2. The voltage Vdd2 is higher than the select voltage Vdd, and the voltage Vdd2 is lower than the program voltage Vpp. Furthermore, the program cycle and the enroll cycle are the same in PUF technology. That is to say, the PUF cell can be enrolled during the enroll action.
During the program cycle, both of the first select transistor S1 and the second select transistor S2 are turned on and both of the first antifuse transistor A1 and the second antifuse transistor A2 receive the program voltage Vpp. Consequently, the state of one of the first antifuse transistor A1 and the second antifuse transistor A2 is changed. For example, the first antifuse transistor A1 is changed to the low resistance state, but the second antifuse transistor A2 is maintained in the high resistance state. Alternatively, the second antifuse transistor A2 is changed to the low resistance state, but the first antifuse transistor A1 is maintained in the high resistance state. Due to the process variations of the antifuse transistors A1 and A2, it is unable to predict which of the antifuse transistors A1 and A2 has the changed state during the program cycle.
During a read cycle, the ground voltage (0V) is provided to the bit line BL, the select voltage Vdd is provided to the word line WL, a read voltage Vr is provided to the first antifuse control line AF1. Moreover, during the read cycle, the bias voltages provided to the word line WL and the read voltage Vr may be in the range between the select voltage Vdd and the voltage Vdd2. The voltage Vdd2 is higher than the select voltage Vdd, and the voltage Vdd2 is lower than the program voltage Vpp.
During the read cycle, the first select transistor S1 and the second select transistor S2 are turned on and the first antifuse transistor A1 generates a read current to the bit line BL. Generally, the read current generated by the first antifuse transistor A1 in the low resistance state is higher, and the read current generated by the first antifuse transistor A1 in the high resistance state is lower. For example, the read current generated by the first antifuse transistor A1 in the low resistance state is 10 pA, and the read current generated by the first antifuse transistor A1 in the high resistance state is 0.1 pA.
Moreover, during the read cycle, a sensing circuit (not shown) determines the storage state of the PUF cell c1 according to the magnitude of the read current from first antifuse transistor A1. In case that the read current generated by the first antifuse transistor A1 is higher, the PUF cell c1 is judged to be in a first storage state. Whereas, in case that the read current generated by the first antifuse transistor A1 is lower, the PUF cell c1 is judged to be in a second storage state.
Due to the process variations of the antifuse transistors A1 and A2, it is unable to predict which of the antifuse transistors A1 and A2 has the changed state during the program cycle. After the PUF cell c1 is programmed, the storage state of the PUF cell c1 is used as a bit of a random code.
Moreover, the random code generator comprises plural PUF cells. After the plural PUF cells are programmed, the random code generator generates a random code according to the storage sates of the plural PUF cells. For example, the random code generator comprises eight PUF cells. After the eight PUF cells are programmed, the random code generator generates a one-byte random code according to the storage sates of the eight PUF cells.
Since the random code is a unique ID code of the semiconductor chip, it is necessary to maintain the accuracy of the random code. If the random code generated by the random code generator is erroneous, the semiconductor chip cannot acquire the protected internal data according to the erroneous random code. In other words, the semiconductor chip cannot be normally operated.